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DAC8043
Rev. E | Page 12 of 16
APPLICATIONS INFORMATION
APPLICATION TIPS
In most applications, linearity depends upon the potential
of the IOUT and GND pins being equal to each other. In most
applications, the DAC is connected to an external op amp
with its noninverting input tied to ground (see Figure 16 and
Figure 17). The amplifier selected should have a low input bias
current and low drift over temperature. The amplifier’s input offset
voltage should be nulled to less than 200 μV (less than 10% of
1 LSB).
The noninverting input of the operational amplifier should have
a minimum resistance connection to ground; the usual bias
current compensation resistor should not be used. This resistor
can cause a variable offset voltage appearing as a varying output
error. All grounded pins should tie to a single common ground
point, avoiding ground loops. The VDD power supply should
have a low noise level with no transients greater than 17 V.
Unipolar Operation (2-Quadrant)
The circuits shown in Figure 16 and Figure 17 may be used with
an ac or dc reference voltage. The output of the circuit ranges
between 0 V and approximately VREF (4095/4096), depending
upon the digital input code. The relationship between the
digital input and the analog output is shown in Table 6. The
limiting parameters for the VREF range are the maximum input
voltage range of the op amp or ±25 V, whichever is lowest.
00271-
016
OP77
DAC8043
3
2
6
4
7
+15V
5V
15pF
VOUT
RFB
VDD
VREF
IOUT
GND
SERIAL
DATA
INPUT
CLK
VREF
10V
–15V
LD
Figure 16. Unipolar Operation with High Accuracy Op Amp (2-Quadrant)
00271-
017
OP42
DAC8043
2
3
6
4
7
+15V
5V
15pF
VOUT
RFB
VDD
VREF
IOUT
GND
SERIAL
DATA
INPUT
CLK
VREF
10V
R2
50
R1
100
–15V
LD
Figure 17. Unipolar Operation with Fast Op Amp and Gain Error Trimming
(2-Quadrant)
Gain error may be trimmed by adjusting R1, as shown in Figure 17.
The DAC register must first be loaded with all 1s. R1 may then
be adjusted until VOUT = VREF (4095/4096). In the case of an
adjustable VREF, R1 and R2 may be omitted, with VREF adjusted
to yield the desired full-scale output.
In most applications, the DAC8043’s negligible zero-scale error
and very low gain error permit the elimination of the trimming
components (R1 and the external R2) without adversely affecting
on circuit performance.
Table 6. Unipolar Code Table1, 2
Digital Input
Nominal Analog Output
MSB
LSB
(V
OUT as Shown in Figure 16 and Figure 17)
1111 1111 1111
4096
4095
REF
V
1000 0000 0001
4096
2049
REF
V
1000 0000 0000
2
4096
2048
REF
V
=
0111 1111 1111
4096
2047
REF
V
0000 0000 0001
4096
1
REF
V
0000 0000 0000
0
4096
0
=
REF
V
1 Nominal full scale for Figure 16 and Figure 17 circuits is given by
=
4096
4095
REF
V
FS
2 Nominal LSB magnitude for Figure 16 and Figure 17 circuits is given by
( )n
REF
V
LSB
=
2
or
4096
1
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